Originally posted by Urban Ranger
The question is, how much will the L3 help when a branch prediction fails and the pipeline gets thrashed? For P4, you're screwed no matter what when the pipeline is emptied and the execution starts over at the other leg. For CPUs with shorter pipes, it's not that bad.
The question is, how much will the L3 help when a branch prediction fails and the pipeline gets thrashed? For P4, you're screwed no matter what when the pipeline is emptied and the execution starts over at the other leg. For CPUs with shorter pipes, it's not that bad.
The extra cache is there to try to lower the memory gap between the Athlon 64 and P4. Athlon 64's memory controller is on-die for low latency (70ns), the P4's for system RAM is somewhere about 90ns right now, but adding cache will lower the average latency even more.
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