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One of the largest "problems" with HyperThreading in today's Pentium 4s is simply that it can't decode enough instructions to keep everything fed.
That's one of the things they've fixed in the Prescott, to improve HyperThreading performance.
Check out this page: http://www.chip-architect.com/news/2..._Prescott.html
Confirmed additions in Prescott:
- A larger L2 Unified Cache: 1024 kByte versus Northwood's 512 kByte
- A larger L1 Data Cache: 16 kByte versus Pentium 4's 8 kByte
- An extremely low clock skew: 7 ps versus 22 ps for Northwood
- 13 new instructions (PNI)
- "La Grande" Support
- Improved Hyper threading technology
- Improved pre-fetcher
- Improved branch predictor
- Improved Integer Multiply latency
- Improved Power management
- Additional Write Combining buffers
And what analysts/hardware geeks have deduced by looking at images of the chip (layout, etc -- not confirmed):
- Instruction Trace Cache extended from 12 to 16 k uOps
- 4 instructions/cycle fetch and retire (up from 3)
- Floating Point unit changed location on the Die
- Two Rapid Execution Engines
- Very wide high speed L3 Cache Bus
- Prescott die size 109 mm^2
A lot of those additions (like the 4 instructions/cycle, dual REE, thread-sync instructions in PNI, increased cache) look like they'll give HyperThreading a big boost.
That's one of the things they've fixed in the Prescott, to improve HyperThreading performance.
Check out this page: http://www.chip-architect.com/news/2..._Prescott.html
Confirmed additions in Prescott:
And what analysts/hardware geeks have deduced by looking at images of the chip (layout, etc -- not confirmed):
A lot of those additions (like the 4 instructions/cycle, dual REE, thread-sync instructions in PNI, increased cache) look like they'll give HyperThreading a big boost.
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