Tweet
This has been widely known for some time thanks to Hans de Vries's excellent analysis of leaked die photos of Prescott. But now, according to The Inquirer, an Intel executive has also confirmed it via word-of-mouth: http://www.theinquirer.net/?article=11668
The hard evidence is already there (by Hans de Vrie)
Should be an interesting couple of months.
Prescott has 64-bit compatibility built in
Needles and pincers
By Charlie Demerjian: Saturday 20 September 2003, 13:07
SINCE WE published the pins and needling story yesterday, the black shirted moles have come out of the woodwork about the innards of Prescott. Those little critters can't stop talking. The power people told us how many pins they needed, months ago, a crazed genius told us about Prescott's die here and here, and lots of people told us that to count said non-power pins. Peeks into the bios code told us more. Motherboard people strongly denied it, and winked at us. Something was up, it was coming from too many directions. Four strong sources, but no smoking gun.
Then, in an anti-climactic burst from out of left field, it all hit at once. Someone came up to me and said 'Guess what I just heard a senior Intel executive say'. Talk about months of hard work ruined by a person who happened on the story of the year. That said, you heard it here first yesterday, Prescott has 64-bit functionality in it. Hans DeVries was dead on.
This answer poses 2 more questions. The first is what instruction set do they use? The AMD64 instruction extensions are theirs to use because of licensing agreements with AMD, but we think they would sooner eat the IDF press room food than do that. MS has been long rumored to tell Intel what they can and can not do, and their record in confrontations like this are not one to bet against. Rumor has it that the vole has said that they will only support a single 64-bit extension to IA32, but then months ago they said they would be supporting 5 64-bit architectures in windows. The mystery deepens.
The more important thing is Itanium. Word on the show floor is that every Intel person thinks that now is the time, and soon they hope to sell more than 4 digits worth (the number of zeros, not the number of fingers, we aren't THAT cynical) of machines in a quarter. The buzz among those with a vested interest is palpable. Performance in a lot of benchmarks is definitely there, but the market still seems to be in the 'dip a toe in' stage. Consumer response, and the response of vendors shows marginal interest.
So the burning question is, will Intel officially tell the world about the 64-bit extensions, and gut the chances of Itanium taking off, or will they sit on it? AMD will most likely determine how and when the 64-bit code gets unveiled, but don't hold your breath. It takes a lot of market share erosion to dump that many years of R&D, and from the looks of it, that isn't happening.
Needles and pincers
By Charlie Demerjian: Saturday 20 September 2003, 13:07
SINCE WE published the pins and needling story yesterday, the black shirted moles have come out of the woodwork about the innards of Prescott. Those little critters can't stop talking. The power people told us how many pins they needed, months ago, a crazed genius told us about Prescott's die here and here, and lots of people told us that to count said non-power pins. Peeks into the bios code told us more. Motherboard people strongly denied it, and winked at us. Something was up, it was coming from too many directions. Four strong sources, but no smoking gun.
Then, in an anti-climactic burst from out of left field, it all hit at once. Someone came up to me and said 'Guess what I just heard a senior Intel executive say'. Talk about months of hard work ruined by a person who happened on the story of the year. That said, you heard it here first yesterday, Prescott has 64-bit functionality in it. Hans DeVries was dead on.
This answer poses 2 more questions. The first is what instruction set do they use? The AMD64 instruction extensions are theirs to use because of licensing agreements with AMD, but we think they would sooner eat the IDF press room food than do that. MS has been long rumored to tell Intel what they can and can not do, and their record in confrontations like this are not one to bet against. Rumor has it that the vole has said that they will only support a single 64-bit extension to IA32, but then months ago they said they would be supporting 5 64-bit architectures in windows. The mystery deepens.
The more important thing is Itanium. Word on the show floor is that every Intel person thinks that now is the time, and soon they hope to sell more than 4 digits worth (the number of zeros, not the number of fingers, we aren't THAT cynical) of machines in a quarter. The buzz among those with a vested interest is palpable. Performance in a lot of benchmarks is definitely there, but the market still seems to be in the 'dip a toe in' stage. Consumer response, and the response of vendors shows marginal interest.
So the burning question is, will Intel officially tell the world about the 64-bit extensions, and gut the chances of Itanium taking off, or will they sit on it? AMD will most likely determine how and when the 64-bit code gets unveiled, but don't hold your breath. It takes a lot of market share erosion to dump that many years of R&D, and from the looks of it, that isn't happening.
Clue 1: The second Integer Unit has no AGU's (Fast double clocked Address Generator Units)
This unit provides the address bits 32 and higher. We will show that there is no need to provide these bits very fast in the NetBurst Architecture with its replay capabilities. nor do we need all bits 32 through 63 A virtual address size of 40 or 48 bits would be sufficient for the time being. (It's 48 bits in the first implementation of the Hammer family)
This unit provides the address bits 32 and higher. We will show that there is no need to provide these bits very fast in the NetBurst Architecture with its replay capabilities. nor do we need all bits 32 through 63 A virtual address size of 40 or 48 bits would be sufficient for the time being. (It's 48 bits in the first implementation of the Hammer family)
Clue 2: The second Integer Unit register file has a smaller size, 1.30 x 0.64 mm versus 1.30 x 0.71 mm
The (renamed) register file of the Pentium 4 has 128 entries for 32 bit data plus 6 bit status flags. We could show that Prescott has two 256 entry register files. The width of the two is equal meaning that they have the same number of entries. The height of the second one is however less, indicating that is has less data bits per entry. We presume that it has all its 32 data bits but that the 6 status flags are lacking. A 64 bit processor needs only one set of status flags per 64 bit word. This clue also implies that the second core can not be used to run an independent 32 bit thread.
The (renamed) register file of the Pentium 4 has 128 entries for 32 bit data plus 6 bit status flags. We could show that Prescott has two 256 entry register files. The width of the two is equal meaning that they have the same number of entries. The height of the second one is however less, indicating that is has less data bits per entry. We presume that it has all its 32 data bits but that the 6 status flags are lacking. A 64 bit processor needs only one set of status flags per 64 bit word. This clue also implies that the second core can not be used to run an independent 32 bit thread.
Clue 3: The data caches have been shifted in order to balance a critical path in 64 bit processing
The first core has to provide the address bits for the data caches of both cores. Most critical in Northwood are bits 6..11 that select one of 32 cache lines in a 2k page and bits 12..16 that are used to predict which of the 4 ways contains the cache line ( 4 x 2kByte = 8 kByte cache size ). These paths should be as short as possible. Going from one core to another introduces a long path for this critical signal. However, it turns out that the path to both caches are equal in length. They managed to do this by shifting both caches upwards.
The first core has to provide the address bits for the data caches of both cores. Most critical in Northwood are bits 6..11 that select one of 32 cache lines in a 2k page and bits 12..16 that are used to predict which of the 4 ways contains the cache line ( 4 x 2kByte = 8 kByte cache size ). These paths should be as short as possible. Going from one core to another introduces a long path for this critical signal. However, it turns out that the path to both caches are equal in length. They managed to do this by shifting both caches upwards.
Should be an interesting couple of months.
Comment